FIG. 1 is a simplified top view of a charge-coupled device (CCD) image sensor according to the prior art. Image sensor 100 includes an array 101 of photosensitive areas 102 arranged in rows and columns. The photosensitive areas 102 collect charge carriers in response to light striking the array 101. Image sensor 100 is illustrated as a full frame image sensor, where photosensitive areas 102 also operate as shift elements in CCD vertical shift registers 104. Accumulated charge packets 106 are shifted one row at a time through the vertical shift registers 104 to the horizontal shift register 108. The charge packets 106 are then serially shifted through the horizontal shift register 108 to an output circuit 110.
Circuit 112 outputs a CCD clocking signal (VCCD) that is transmitted to output circuit 110 on signal line 114. The CCD clocking signal (VCCD) is input into a low to medium capacitance clock input that is used to reset a charge storage element to a known potential or voltage level. For example, a reset transistor 200 (see FIG. 2) can be included in output circuit 110, and the CCD clocking signal (VCCD) is received on the gate 202 of the reset transistor. The low to medium capacitance clock input includes the gate of the reset transistor 200. The charge storage element to be reset to a known potential (e.g., element 204) can be implemented as the last shift element 116 in horizontal shift register 108 or as a floating diffusion that receives charge from shift element 116.
FIG. 3 is a schematic diagram of a first circuit for producing a clocking signal for a capacitance clock input in accordance with the prior art. Drive gate 300 receives an input signal VIN, inverts the VIN signal, and outputs a clocking signal VCCD. Drive gate 300 is power efficient and very fast, but is limited in the voltage swing it can produce. Generally, the voltage swing of drive gate 300 is limited to six volts due to the maximum supply voltage (VCC) rating.
FIG. 4 is a schematic diagram of a second circuit for producing a clocking signal for a capacitance clock input in accordance with the prior art. Circuit 400 includes drive gate 300 connected to a common-emitter bipolar driver circuit 402. Circuit 400 has good power efficiency and is capable of producing a larger voltage swing in VCCD than drive gate 300 is able to produce by itself. For example, the voltage swing for circuit 400 can be ten volts. But circuit 400 suffers from waveform distortion and speed limitations due to the inverting character of circuit 400.
FIG. 5 is a schematic diagram of a third circuit for producing a clocking signal for a capacitance clock input in accordance with the prior art. Circuit 500 uses two metal oxide semiconductor field-effect transistors 502, 504 (MOSFET) instead of NPN and PNP bi-polar transistors 404, 406 shown in FIG. 4. Circuit 500 operates more quickly and can produce even larger voltage swings than circuit 400. But circuit 500 suffers from waveform distortion, and due to the unavailability of small enough MOSFETS, requires too much gate drive power to use at frequencies above 25 MHz.